The effects of radiation on integrated circuits have been known for over thirty years. These effects can be broken down into two broad categories. The first category is “total dose effects” in which an integrated circuit gradually deteriorates due to the accumulated effect of all the damage done to the crystal structure by the many, many particles incident on it. In the 1980s and early 90s, these effects were mitigated by special “rad hard” processes. These rad hard processes were expensive because they required special processing steps to fabricate. Fortunately, the unstoppable drive towards smaller and smaller transistor sizes has allowed those skilled in the art to develop “radiation tolerant” layout techniques in deep sub-micron processes that are the cornerstone of modern silicon fabrication. These radiation tolerant layout techniques mitigate total dose effects at least as well if not better than the “rad hard” processes ever did. Moreover, the fact that radiation tolerant layout techniques use standard silicon processing makes them inexpensive and available to everyone. For these reasons, total dose harness can be viewed as a solved problem, though radiation tolerant layout techniques place restrictions on a designer's freedom, most notably on his or her ability to ratio transistors at will.
The second category of radiation effects is “single event effects” in which a single particle, either through its exceptionally high energy or through the accuracy of its trajectory through a semiconductor, is capable of affecting a circuit. Single event effects are varied, and most of the effects can be mitigated by proper layout techniques. One type of single-event effect in particular requires more effort to eliminate, however, and that is the single event upset or SEU in which the contents of a memory cell are altered by an incident particle.
SEUs belong to a class of errors called “soft-errors” in that they simply reverse the state of a memory. They do not, in and of themselves, damage a circuit. This does not mean, however, that they can be ignored. Single event upsets in a computer alter the computer's internal state, “confusing” the computer and potentially crashing the system. In the case of computers that control satellite systems or machinery, this can be catastrophic. Single event upsets in medical imaging and scientific experiment can result in noisy signals and data loss, requiring higher intensities and longer exposure times to overcome the noise.
A number of SEU-hardening techniques have been employed in the past. These techniques can be divided into three types. The first type is technology hardening in which changes are made to the fabrication of the chip such that critical charges necessary for single-event upset to occur do so with reduced frequency. One example of technology hardening is Silicon-on-Sapphire or SOS in which the chip is grown on an insulator to reduce the charge build-up due to incident particles. The second type of SEU hardening is passive hardening in which passive components like capacitors or resistors are added to a circuit to either slow it down or to increase the charge required to reverse its state. Finally, the third type of SEU hardening is design hardening in which redundancy and feedback are added to a circuit to make it immune to single events.
Technology hardening is not generally viable commercially because the silicon industry has become accustomed to its fabrication methods for which it has spent billions of dollars to develop. Passive hardening is not efficient. Although it is a workable solution, it is a deliberate slowing-down of information processing, which is at odds with the clear industry objective to speed up processing. Moreover, passive hardening is not scalable, therefore fabrication changes from 0.5 μm to 0.25 μm to 0.18 μm requires passive hardening redesign and re-testing. Design hardening, on the other hand, is limited only by the creativity of the designers.
Computer memory comes in different forms. The two most common categories are SRAM and DRAM. Both are ubiquitous in modern digital design. DRAM or Dynamic Random Access Memory is smaller and generally slower. They are used for mass storage and their contents must continually be refreshed or the values they hold will be lost. SRAM or Static Random Access Memory is larger and faster and they will hold their contents indefinitely without external intervention. Both types of memory are subject to radiation effects.
Most single event upset tolerant SRAM cells (hereinafter “cells”) are clocked, D-type latches, which is to say that they obey the logical flow shown in Table 1. In short, when Clock is low, Next State equals Previous State. When Clock is High, Next State equals Data. Per se, there is nothing wrong with a D-type latch. It is the single most common type of latch since the dawn of the ASIC age. It is not the only type of latch however.
TABLE 1Logical Flow of a Clocked, D-LatchInputPresentNextClockDataStateState00000011010001111000101011011111
Another common type of latch is the SR or Set-Reset Latch. These latches obey the logical flow shown in Table 2. In short, when Set is active and Reset is inactive, regardless of the present state, the latch changes its state to a 1. When Reset is active and Set is inactive, regardless of the present state, the latch changes its state to a 0. When Set and Reset are both inactive, the latch holds the present state. Finally, Set and Reset are not allowed to be active simultaneously. Note that in these preceding sentences, Set and Reset are referred to as being either “active” or “inactive” rather than explicitly “1” or “0”. This is the concept of positive logic or negative logic and it is important for SR-Latches. Positive Logic means a 1 is active and a 0 is inactive. Negative Logic means a 0 is active and a 1 is inactive. Therefore, Table 2 actually shows the Logical Flow of a Positive Logic SR-Latch. The Logical Flow of a Negative Logic SR-Latch is identical except that a 1 is substituted for every 0 in both the S and R columns (but not the Present State or Next State columns) and a 0 is substituted for every 1 in both the S and R columns (but not the Present State or Next State columns).
TABLE 2Logical Flow of an SR-Latch(Positive Logic)PresentNextSRStateState000000110100011010011011110U111U
Two fundamental building blocks of logic design are the Nand gate and the Nor gate. The Nand or “not and” gate obeys the logical flow shown in Table 3. The Nor or “Not or” gate obeys the logical flow shown in Table 4.
TABLE 3Logical Flow of a Nand GateABA AND BNAND(A, B)0001010110011110
TABLE 4Logical Flow of a Nand GateABA OR BNOR(A, B)0001011010101110
In logic design, a negative logic canonical SR flip-flop is formed by cross-coupling Nand gates as shown in FIG. 1A. A canonical positive logic SR flip-flop is formed by cross-coupling Nor gates as shown in FIG. 1B.
SR flip-flops are considered the fundamental building blocks of sequential design (i.e. logic design with memory). D-latches are common in modern ASIC design because 1) the specialized computer industry generally want to latch and hold data and that is what a D-latch does and 2) D-latches can easily be designed in modern integrated circuit processes. SR latches are more fundamental than D-latches, however, because you can convert an SR-latch into a D-latch with one external gate, but you cannot convert a D-latch into an SR latch. You can convert an SR-latch into a clocked D-latch with three external gates. In short, an SR-latch can be converted into any other type of latch with a simple application of external logic. From a logic designer's point of view, the SR latch is easily the most flexible type of latch available.
Although there are two categories of radiation effects, total dose and single event, neither category are necessarily lumped together. There are instances when applications require single event immunity but not necessarily total dose immunity (such as a device that is only going to be exposed to radiation for a short time (e.g., X-ray detectors for medical imaging) and there are instances when applications require total dose immunity but not single event immunity. Nevertheless, it is most typical that a device be both total dose and single event tolerant. Unfortunately, many existing single event upset tolerant SRAM cells were designed for rad hard processes and they accomplish their SEU tolerance through highly specific transistor ratioing. This is to say that, in order for the circuits to function properly, certain transistors must be made weak and others must be made very strong. This adjusting of transistor strength is called “transistor ratioing” because the ratio of the size of two transistors determines their relative strength.
As stated earlier, radiation tolerant design techniques in deep submicron processes are very effective, but they dramatically limit a designer's freedom to ratio his or her transistors and because of that, they also limit the number of SEU tolerant architectures that can be designed using radiation tolerant techniques. Some existing cells can be re-designed such that the burden of ratioing is born entirely by the p-type transistors, which are unaffected by the limitations imposed by radiation tolerant layout techniques. If a particular SEU tolerant architecture requires ratioing of its n-type transistors, however, then the chances are very good that SEU tolerant architecture simply cannot be realized in a modern, cost-effective integrated circuit process. Moreover, if a cell requires ratioing to accomplish its objectives (even ratioing of its p-type transistors), then the speed, size, power consumption, and, ultimately, SEU tolerance of that cell will be intimately related to the ratios chosen by the designer. This will be an issue whenever the device is scaled from one technology to another. Scaling from one process to another, (e.g., changing from 0.25 μm to 0.18 μm), can be problematic. Scaling problems are rarely insurmountable, but improperly scaled circuits are often the cause of failure in technology transfers. Few cells can be designed exclusively with minimum-sized transistors.
Many cells require that the internal state of the cell be overdriven by external circuitry. For example, the DICE cell 200, which is labeled as “prior art” and is illustrated in FIG. 2 shows that either transistor P2 (if the cell is holding a 1) or transistor N2 (if the cell is holding a 0) are driving Node A. Similarly, either transistor P4 or transistor N4 is driving Node B. When CLK is active, both Node A and Node B will be connected to Node D, and whatever external circuit is driving Node D will have to overcome the strength of the transistors driving Nodes A and B if it is to change the internal state of the DICE cell. This phenomenon is called overdriving. First when circuits must be overdriven, it underscores the necessity of transistor ratioing.
External transistors must be more powerful (i.e., larger) than the transistors inside the cell. This can be troublesome in a shift register configuration or even a master-slave flip-flop configuration when one cell is driving another of the same type. If both the master and the slave are of the same type, then, by definition, the transistors in the external circuitry (the master) are not larger than the transistors inside the cell (the slave). Second, overdriving requires power when changing a state. The external transistors must drive the internal nodes to the reverse condition even though the internal transistors are trying to maintain their original condition. Accordingly, the power and ground are briefly shorted to one another through the internal and external transistors.
Most cells cannot be asynchronously set or reset without undesirable modifications to their internal structure. In the past, if a set or a reset were required, they were carried out synchronously—in other words, in the presence of a clock. This is not always the best approach for system designs. In fact, many systems require considerable work to guarantee a synchronous reset. Moreover, in the absence of a clock, a synchronously reset system cannot be reset. Therefore, if the clock itself is the problem, there is no way of recovering to a known state. Asynchronous sets and resets are, by a wide margin, the preferred approach by many organizations working in high radiation environments, and virtually all industrial applications in non-radiation environments.
Most existing SEU tolerant cells perform the job they are designed to do, to a greater or lesser degree. In other words, they store data and they mitigate single event upsets. All cells, however, suffer from limitations. It would therefore be desirable to have SEU tolerant circuits that are more flexible logically, require no transistor ratios and could be designed in the minimum sized transistors available to any process, are designable in either specifically Rad hard processes or standard commercial processes or standard commercial processes using radiation tolerant layout techniques, are inherently scalable from process to process, require no overdriving of its internal state, and permit asynchronous sets and resets.